OpenCores
URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [BUGS.txt] - Rev 17

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 Fix ABX, TST, implemented new decoder, removed unused logic ale500 3634d 12h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
12 Fixed inc, dec, indirect indexed, mul, shifts, h flag ale500 3658d 17h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
10 Fixed several extended and indirect opcodes ale500 3665d 17h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
9 Implemented E flag, some minor optimizations ale500 3839d 17h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
7 Added SYNC, Fixed EXG ale500 3840d 16h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
6 Implemented CWAI. Minor optimizations ale500 3844d 13h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
5 EXG/TFR Implemented ale500 3845d 10h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
4 Bugfix and enhancements ale500 3846d 15h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt
2 Initial version ale500 3848d 13h /6809_6309_compatible_core/trunk/rtl/verilog/BUGS.txt

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.