URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] [verilog/] [oc8051_tb.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5572d 20h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
185		root	5628d 21h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7757d 19h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
124	add support for external rom from xilinx ramb4	simont	7784d 01h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
120	defines for pherypherals added	simont	7789d 23h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
111	Remove instruction cache and wb_interface	simont	7796d 16h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
103	rename signals	simont	7797d 20h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
84	remove wb_bus_mon	simont	7876d 21h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
74	add module oc8051_wb_iinterface	simont	7953d 19h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
68	add instruction cache and DELAY parameters for external ram, rom	simont	7957d 22h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
59	add external rom	simont	7964d 16h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
46	prepared header	simont	7981d 18h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
37	added signals ack, stb and cyc	simont	8008d 20h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
4	Code repaired to satisfy the linter; testbech fails	markom	8029d 00h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v
2	Initial CVS import	simont	8044d 22h	/8051/tags/rel_1/bench/verilog/oc8051_tb.v