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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_alu.v] - Rev 186

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186 root 5543d 13h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
185 root 5599d 14h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7728d 12h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
143 add wire sub_result, conect it to des_acc and des1. simont 7733d 16h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
139 add aditional alu destination to solve critical path. simont 7735d 13h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
133 fix bug in substraction. simont 7741d 20h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
132 change branch instruction execution (reduse needed clock periods). simont 7745d 11h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
123 fiz bug iv pcs operation. simont 7756d 14h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
82 replace some modules simont 7847d 14h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
46 prepared header simont 7952d 11h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
22 fix some bugs simont 7992d 09h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
11 des2_r removed simont 7997d 13h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
10 % replaced with ^ in uart; some minor improvements markom 7997d 19h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
8 some IDS optimizations markom 7999d 12h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 7999d 13h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
5 more linter corrections; 2 tests still fail markom 7999d 15h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
4 Code repaired to satisfy the linter; testbech fails markom 7999d 17h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v
2 Initial CVS import simont 8015d 15h /8051/tags/rel_1/rtl/verilog/oc8051_alu.v

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