URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_b_register.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5533d 00h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
185		root	5589d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7717d 23h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
118	change wr_sft to 2 bit wire.	simont	7750d 23h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
116	change sfr's interface.	simont	7753d 01h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
82	replace some modules	simont	7837d 01h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
46	prepared header	simont	7941d 22h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
27	fix some bugs	simont	7980d 05h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
22	fix some bugs	simont	7981d 20h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
5	more linter corrections; 2 tests still fail	markom	7989d 03h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
4	Code repaired to satisfy the linter; testbech fails	markom	7989d 04h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v
2	Initial CVS import	simont	8005d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_b_register.v