URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_comp.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5543d 14h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
185		root	5599d 15h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7728d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
132	change branch instruction execution (reduse needed clock periods).	simont	7745d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
95	updating...	simont	7768d 18h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
46	prepared header	simont	7952d 11h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
16	inputs ram and op2 removed	simont	7996d 15h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
10	% replaced with ^ in uart; some minor improvements	markom	7997d 19h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
9	removed unused compare states	markom	7999d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v
2	Initial CVS import	simont	8015d 15h	/8051/tags/rel_1/rtl/verilog/oc8051_comp.v