OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_defines.v] - Rev 186

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5533d 00h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
185 root 5589d 01h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7717d 23h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7724d 05h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
139 add aditional alu destination to solve critical path. simont 7724d 23h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
132 change branch instruction execution (reduse needed clock periods). simont 7734d 22h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
126 define OC8051_XILINX_RAMB added simont 7744d 05h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
122 deifne OC8051_ROM added simont 7749d 05h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
120 defines for pherypherals added simont 7750d 02h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
118 change wr_sft to 2 bit wire. simont 7750d 23h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
114 remove t2mod register simont 7756d 05h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
93 OC8051_XILINX_RAM added simont 7758d 04h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
82 replace some modules simont 7837d 01h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
67 add parameters for instruction cache simont 7918d 02h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
9 removed unused compare states markom 7988d 23h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v
2 Initial CVS import simont 8005d 02h /8051/tags/rel_1/rtl/verilog/oc8051_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.