URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5543d 13h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
185		root	5599d 14h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7728d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
146	fix bug in movc intruction.	simont	7728d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
140	cahnge assigment to pc_wait (remove istb_o)	simont	7734d 19h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
139	add aditional alu destination to solve critical path.	simont	7735d 13h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
132	change branch instruction execution (reduse needed clock periods).	simont	7745d 11h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
128	chance idat_ir to 24 bit wide	simont	7754d 18h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
121	Change pc add value from 23'h to 16'h	simont	7759d 18h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
118	change wr_sft to 2 bit wire.	simont	7761d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v
81	initial import	simont	7847d 14h	/8051/tags/rel_1/rtl/verilog/oc8051_memory_interface.v