URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_ports.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5543d 13h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
185		root	5599d 14h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7728d 12h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
120	defines for pherypherals added	simont	7760d 16h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
116	change sfr's interface.	simont	7763d 13h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
82	replace some modules	simont	7847d 14h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
46	prepared header	simont	7952d 11h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
22	fix some bugs	simont	7992d 09h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
15	commbinatorial loop removed	simont	7996d 15h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
5	more linter corrections; 2 tests still fail	markom	7999d 15h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
4	Code repaired to satisfy the linter; testbech fails	markom	7999d 17h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v
2	Initial CVS import	simont	8015d 15h	/8051/tags/rel_1/rtl/verilog/oc8051_ports.v