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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

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186 root 5543d 13h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
185 root 5599d 15h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7728d 12h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7733d 16h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7734d 19h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7735d 13h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7741d 17h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7745d 11h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7759d 19h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7760d 16h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7761d 12h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7761d 13h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7767d 09h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
102 raname signals. simont 7768d 13h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
82 replace some modules simont 7847d 14h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7916d 11h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7924d 14h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7929d 12h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7935d 10h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
46 prepared header simont 7952d 11h /8051/tags/rel_1/rtl/verilog/oc8051_top.v

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