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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Rev 186

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186 root 5543d 13h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
185 root 5599d 15h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7728d 12h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
135 prepared start of receiving if ren is not active. simont 7741d 17h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
119 remove signal sbuf_txd [12:11] simont 7760d 20h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
116 change sfr's interface. simont 7763d 14h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
115 change uart to meet timing. simont 7763d 15h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
82 replace some modules simont 7847d 14h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
46 prepared header simont 7952d 11h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
36 fix bugs in mode 0 simont 7979d 14h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7990d 17h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
17 fix some bugs simont 7996d 15h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
10 % replaced with ^ in uart; some minor improvements markom 7997d 19h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
8 some IDS optimizations markom 7999d 12h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
5 more linter corrections; 2 tests still fail markom 7999d 16h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
4 Code repaired to satisfy the linter; testbech fails markom 7999d 17h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v
2 Initial CVS import simont 8015d 15h /8051/tags/rel_1/rtl/verilog/oc8051_uart.v

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