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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Rev 186

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186 root 5543d 13h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
185 root 5599d 14h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7728d 12h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
138 Change buffering to save one clock per instruction. simont 7735d 13h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
136 registering outputs. simont 7735d 18h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
127 fix bug (cyc_o and stb_o) simont 7754d 18h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
110 change adr_i and adr_o length. simont 7767d 09h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
82 replace some modules simont 7847d 14h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v
73 initial import simont 7924d 12h /8051/tags/rel_1/rtl/verilog/oc8051_wb_iinterface.v

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