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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 186

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186 root 5531d 07h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
185 root 5587d 08h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7666d 00h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
179 add /* synopsys xx_case */ to case statments. simont 7666d 01h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
149 pipelined acces to axternal instruction interface added. simont 7694d 05h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
142 optimize state machine. simont 7722d 11h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7722d 12h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
139 add aditional alu destination to solve critical path. simont 7723d 06h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
132 change branch instruction execution (reduse needed clock periods). simont 7733d 05h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
118 change wr_sft to 2 bit wire. simont 7749d 05h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7749d 06h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
82 replace some modules simont 7835d 08h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
62 fix bugs in instruction interface simont 7917d 05h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
54 cahnge interface to instruction rom simont 7923d 03h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
46 prepared header simont 7940d 04h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
40 added sigals for interacting with external ram simont 7960d 08h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
23 mul & div use 4 clocks simont 7980d 02h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
20 multiplier and divider changed so they complete in 4 cycles markom 7980d 10h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
17 fix some bugs simont 7984d 08h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
10 % replaced with ^ in uart; some minor improvements markom 7985d 12h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v

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