URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_icache.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5531d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
185		root	5587d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7666d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
179	add /* synopsys xx_case */ to case statments.	simont	7666d 01h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
174	ram modules added.	simont	7677d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
137	change to fit xrom.	simont	7723d 11h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
108	fix some bugs, use oc8051_cache_ram.	simont	7755d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
94	fix bug.	simont	7756d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
88	fix bugs	simont	7827d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
82	replace some modules	simont	7835d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
67	add parameters for instruction cache	simont	7916d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
62	fix bugs in instruction interface	simont	7917d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v