URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_indi_addr.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5531d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
185		root	5587d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7665d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
179	add /* synopsys xx_case */ to case statments.	simont	7666d 01h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
139	add aditional alu destination to solve critical path.	simont	7723d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
82	replace some modules	simont	7835d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
46	prepared header	simont	7940d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
5	more linter corrections; 2 tests still fail	markom	7987d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
4	Code repaired to satisfy the linter; testbech fails	markom	7987d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v
2	Initial CVS import	simont	8003d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_indi_addr.v