URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_multiply.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5531d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
185		root	5587d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7666d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
95	updating...	simont	7756d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
46	prepared header	simont	7940d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
32	overflow repaired	simont	7968d 11h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
25	divider and multiplier pass test	markom	7979d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
21	mul bug fixed	markom	7980d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
20	multiplier and divider changed so they complete in 4 cycles	markom	7980d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
5	more linter corrections; 2 tests still fail	markom	7987d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
4	Code repaired to satisfy the linter; testbech fails	markom	7987d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
2	Initial CVS import	simont	8003d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v