URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_ram_top.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5531d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
185		root	5587d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7666d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
177	Fix bug in case of writing and reading from same address.	simont	7677d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
174	ram modules added.	simont	7677d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
172	BIST signals added.	simont	7680d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
105	generic_dpram used	simont	7756d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
95	updating...	simont	7756d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
89	Replaced oc8051_ram by generic_dpram.	rherveille	7822d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
82	replace some modules	simont	7835d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
46	prepared header	simont	7940d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
41	remove unused files	simont	7940d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
4	Code repaired to satisfy the linter; testbech fails	markom	7987d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
2	Initial CVS import	simont	8003d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v