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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_tc.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5614d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
185		root	5670d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7749d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
179	add /* synopsys xx_case */ to case statments.	simont	7749d 17h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
120	defines for pherypherals added	simont	7832d 01h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
116	change sfr's interface.	simont	7834d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
112	change timers to meet timing specifications (add divider with 12)	simont	7838d 03h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
82	replace some modules	simont	7918d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
46	prepared header	simont	8023d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
17	fix some bugs	simont	8068d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
4	Code repaired to satisfy the linter; testbech fails	markom	8071d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
2	Initial CVS import	simont	8087d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v