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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

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186 root 5531d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
185 root 5587d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7665d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
181 Simulation reports added. simont 7665d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
174 ram modules added. simont 7677d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
172 BIST signals added. simont 7680d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7694d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7721d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7722d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7723d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7729d 10h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7733d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7747d 11h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7748d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7749d 05h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7749d 05h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7755d 02h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
102 raname signals. simont 7756d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
82 replace some modules simont 7835d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7904d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

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