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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Rev 186

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186 root 5531d 06h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
185 root 5587d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7666d 00h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
179 add /* synopsys xx_case */ to case statments. simont 7666d 01h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
135 prepared start of receiving if ren is not active. simont 7729d 10h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
119 remove signal sbuf_txd [12:11] simont 7748d 13h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
116 change sfr's interface. simont 7751d 07h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
115 change uart to meet timing. simont 7751d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
82 replace some modules simont 7835d 07h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
46 prepared header simont 7940d 04h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
36 fix bugs in mode 0 simont 7967d 07h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7978d 10h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
17 fix some bugs simont 7984d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
10 % replaced with ^ in uart; some minor improvements markom 7985d 12h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
8 some IDS optimizations markom 7987d 05h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
5 more linter corrections; 2 tests still fail markom 7987d 09h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
4 Code repaired to satisfy the linter; testbech fails markom 7987d 10h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
2 Initial CVS import simont 8003d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v

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