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[/] [8051/] [tags/] [rel_2/] [bench/] [verilog/] [oc8051_tb.v] - Rev 186

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Rev Log message Author Age Path
186 root 5543d 14h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
185 root 5599d 16h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7678d 09h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
167 add readmem for ea. simont 7703d 19h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
166 Change test monitor from ports to external data memory. simont 7704d 12h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
165 remove dumpvars. simont 7704d 17h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
156 add FREQ paremeter. simont 7704d 18h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
124 add support for external rom from xilinx ramb4 simont 7754d 20h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
120 defines for pherypherals added simont 7760d 17h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
111 Remove instruction cache and wb_interface simont 7767d 10h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
103 rename signals simont 7768d 15h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
84 remove wb_bus_mon simont 7847d 15h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
74 add module oc8051_wb_iinterface simont 7924d 13h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
68 add instruction cache and DELAY parameters for external ram, rom simont 7928d 16h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
59 add external rom simont 7935d 11h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
46 prepared header simont 7952d 12h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
37 added signals ack, stb and cyc simont 7979d 15h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
4 Code repaired to satisfy the linter; testbech fails markom 7999d 18h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
2 Initial CVS import simont 8015d 16h /8051/tags/rel_2/bench/verilog/oc8051_tb.v

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