URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] [verilog/] [oc8051_comp.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5572d 22h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
185		root	5628d 23h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7707d 17h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
179	add /* synopsys xx_case */ to case statments.	simont	7707d 17h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
132	change branch instruction execution (reduse needed clock periods).	simont	7774d 20h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
95	updating...	simont	7798d 02h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
46	prepared header	simont	7981d 20h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
16	inputs ram and op2 removed	simont	8026d 00h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
10	% replaced with ^ in uart; some minor improvements	markom	8027d 04h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
9	removed unused compare states	markom	8028d 21h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v
2	Initial CVS import	simont	8045d 00h	/8051/tags/rel_2/rtl/verilog/oc8051_comp.v