URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] [verilog/] [oc8051_divide.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5530d 17h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
185		root	5586d 18h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7665d 11h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
95	updating...	simont	7755d 21h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
45	prepared header	simont	7939d 15h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
29	fix some bugs	simont	7977d 21h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7977d 23h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
25	divider and multiplier pass test	markom	7978d 18h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
20	multiplier and divider changed so they complete in 4 cycles	markom	7979d 21h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
5	more linter corrections; 2 tests still fail	markom	7986d 19h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
4	Code repaired to satisfy the linter; testbech fails	markom	7986d 21h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
2	Initial CVS import	simont	8002d 19h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v