URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] [verilog/] [oc8051_divide.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5572d 22h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
185		root	5628d 23h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7707d 17h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
95	updating...	simont	7798d 02h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
45	prepared header	simont	7981d 20h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
29	fix some bugs	simont	8020d 02h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8020d 04h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
25	divider and multiplier pass test	markom	8020d 23h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
20	multiplier and divider changed so they complete in 4 cycles	markom	8022d 02h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
5	more linter corrections; 2 tests still fail	markom	8029d 01h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
4	Code repaired to satisfy the linter; testbech fails	markom	8029d 02h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v
2	Initial CVS import	simont	8045d 00h	/8051/tags/rel_2/rtl/verilog/oc8051_divide.v