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[/] [8051/] [tags/] [rel_2/] [rtl/] [verilog/] [oc8051_sfr.v] - Rev 186

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186 root 5572d 22h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
185 root 5628d 23h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7707d 16h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
179 add /* synopsys xx_case */ to case statments. simont 7707d 16h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
145 fix bug in case of sequence of inc dptr instrucitons. simont 7763d 00h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
139 add aditional alu destination to solve critical path. simont 7764d 21h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
134 fix bug in case execution of two data dependent instructions. simont 7771d 01h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
132 change branch instruction execution (reduse needed clock periods). simont 7774d 20h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
120 defines for pherypherals added simont 7790d 00h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
118 change wr_sft to 2 bit wire. simont 7790d 20h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7790d 21h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
116 change sfr's interface. simont 7792d 22h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
115 change uart to meet timing. simont 7792d 23h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
113 signal prsc_ow added. simont 7796d 02h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
90 change module name. simont 7802d 19h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
87 add include oc8051_defines.v simont 7868d 23h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
82 replace some modules simont 7876d 23h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v
75 initial import simont 7945d 19h /8051/tags/rel_2/rtl/verilog/oc8051_sfr.v

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