URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5530d 17h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
185		root	5586d 18h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7665d 11h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
138	Change buffering to save one clock per instruction.	simont	7722d 16h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
136	registering outputs.	simont	7722d 21h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
127	fix bug (cyc_o and stb_o)	simont	7741d 22h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
110	change adr_i and adr_o length.	simont	7754d 13h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
82	replace some modules	simont	7834d 18h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v
73	initial import	simont	7911d 15h	/8051/tags/rel_2/rtl/verilog/oc8051_wb_iinterface.v