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[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_tb.v] - Rev 186

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Rev Log message Author Age Path
186 root 5624d 07h /8051/trunk/bench/verilog/oc8051_tb.v
185 root 5680d 08h /8051/trunk/bench/verilog/oc8051_tb.v
167 add readmem for ea. simont 7784d 12h /8051/trunk/bench/verilog/oc8051_tb.v
166 Change test monitor from ports to external data memory. simont 7785d 05h /8051/trunk/bench/verilog/oc8051_tb.v
165 remove dumpvars. simont 7785d 09h /8051/trunk/bench/verilog/oc8051_tb.v
156 add FREQ paremeter. simont 7785d 11h /8051/trunk/bench/verilog/oc8051_tb.v
124 add support for external rom from xilinx ramb4 simont 7835d 12h /8051/trunk/bench/verilog/oc8051_tb.v
120 defines for pherypherals added simont 7841d 10h /8051/trunk/bench/verilog/oc8051_tb.v
111 Remove instruction cache and wb_interface simont 7848d 03h /8051/trunk/bench/verilog/oc8051_tb.v
103 rename signals simont 7849d 07h /8051/trunk/bench/verilog/oc8051_tb.v
84 remove wb_bus_mon simont 7928d 08h /8051/trunk/bench/verilog/oc8051_tb.v
74 add module oc8051_wb_iinterface simont 8005d 06h /8051/trunk/bench/verilog/oc8051_tb.v
68 add instruction cache and DELAY parameters for external ram, rom simont 8009d 09h /8051/trunk/bench/verilog/oc8051_tb.v
59 add external rom simont 8016d 03h /8051/trunk/bench/verilog/oc8051_tb.v
46 prepared header simont 8033d 05h /8051/trunk/bench/verilog/oc8051_tb.v
37 added signals ack, stb and cyc simont 8060d 07h /8051/trunk/bench/verilog/oc8051_tb.v
4 Code repaired to satisfy the linter; testbech fails markom 8080d 11h /8051/trunk/bench/verilog/oc8051_tb.v
2 Initial CVS import simont 8096d 09h /8051/trunk/bench/verilog/oc8051_tb.v

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