URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_tb.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5645d 18h	/8051/trunk/bench/verilog/oc8051_tb.v
185		root	5701d 19h	/8051/trunk/bench/verilog/oc8051_tb.v
167	add readmem for ea.	simont	7805d 23h	/8051/trunk/bench/verilog/oc8051_tb.v
166	Change test monitor from ports to external data memory.	simont	7806d 16h	/8051/trunk/bench/verilog/oc8051_tb.v
165	remove dumpvars.	simont	7806d 20h	/8051/trunk/bench/verilog/oc8051_tb.v
156	add FREQ paremeter.	simont	7806d 22h	/8051/trunk/bench/verilog/oc8051_tb.v
124	add support for external rom from xilinx ramb4	simont	7856d 23h	/8051/trunk/bench/verilog/oc8051_tb.v
120	defines for pherypherals added	simont	7862d 20h	/8051/trunk/bench/verilog/oc8051_tb.v
111	Remove instruction cache and wb_interface	simont	7869d 14h	/8051/trunk/bench/verilog/oc8051_tb.v
103	rename signals	simont	7870d 18h	/8051/trunk/bench/verilog/oc8051_tb.v
84	remove wb_bus_mon	simont	7949d 18h	/8051/trunk/bench/verilog/oc8051_tb.v
74	add module oc8051_wb_iinterface	simont	8026d 16h	/8051/trunk/bench/verilog/oc8051_tb.v
68	add instruction cache and DELAY parameters for external ram, rom	simont	8030d 19h	/8051/trunk/bench/verilog/oc8051_tb.v
59	add external rom	simont	8037d 14h	/8051/trunk/bench/verilog/oc8051_tb.v
46	prepared header	simont	8054d 15h	/8051/trunk/bench/verilog/oc8051_tb.v
37	added signals ack, stb and cyc	simont	8081d 18h	/8051/trunk/bench/verilog/oc8051_tb.v
4	Code repaired to satisfy the linter; testbech fails	markom	8101d 22h	/8051/trunk/bench/verilog/oc8051_tb.v
2	Initial CVS import	simont	8117d 19h	/8051/trunk/bench/verilog/oc8051_tb.v