URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_b_register.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5680d 16h	/8051/trunk/rtl/verilog/oc8051_b_register.v
185		root	5736d 17h	/8051/trunk/rtl/verilog/oc8051_b_register.v
118	change wr_sft to 2 bit wire.	simont	7898d 14h	/8051/trunk/rtl/verilog/oc8051_b_register.v
116	change sfr's interface.	simont	7900d 16h	/8051/trunk/rtl/verilog/oc8051_b_register.v
82	replace some modules	simont	7984d 17h	/8051/trunk/rtl/verilog/oc8051_b_register.v
46	prepared header	simont	8089d 13h	/8051/trunk/rtl/verilog/oc8051_b_register.v
27	fix some bugs	simont	8127d 20h	/8051/trunk/rtl/verilog/oc8051_b_register.v
22	fix some bugs	simont	8129d 12h	/8051/trunk/rtl/verilog/oc8051_b_register.v
5	more linter corrections; 2 tests still fail	markom	8136d 18h	/8051/trunk/rtl/verilog/oc8051_b_register.v
4	Code repaired to satisfy the linter; testbech fails	markom	8136d 20h	/8051/trunk/rtl/verilog/oc8051_b_register.v
2	Initial CVS import	simont	8152d 17h	/8051/trunk/rtl/verilog/oc8051_b_register.v