URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5680d 19h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
185		root	5736d 20h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
181	Simulation reports added.	simont	7815d 13h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
179	add /* synopsys xx_case */ to case statments.	simont	7815d 14h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
173	simualtion `ifdef added	simont	7826d 21h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
158	fix bug.	simont	7841d 23h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
149	pipelined acces to axternal instruction interface added.	simont	7843d 17h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
146	fix bug in movc intruction.	simont	7865d 18h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
140	cahnge assigment to pc_wait (remove istb_o)	simont	7872d 01h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
139	add aditional alu destination to solve critical path.	simont	7872d 19h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
132	change branch instruction execution (reduse needed clock periods).	simont	7882d 17h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
128	chance idat_ir to 24 bit wide	simont	7892d 00h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
121	Change pc add value from 23'h to 16'h	simont	7897d 00h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
118	change wr_sft to 2 bit wire.	simont	7898d 18h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
81	initial import	simont	7984d 20h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v