URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5676d 18h	/8051/trunk/rtl/verilog/oc8051_uart.v
185		root	5732d 19h	/8051/trunk/rtl/verilog/oc8051_uart.v
179	add /* synopsys xx_case */ to case statments.	simont	7811d 13h	/8051/trunk/rtl/verilog/oc8051_uart.v
135	prepared start of receiving if ren is not active.	simont	7874d 22h	/8051/trunk/rtl/verilog/oc8051_uart.v
119	remove signal sbuf_txd [12:11]	simont	7894d 00h	/8051/trunk/rtl/verilog/oc8051_uart.v
116	change sfr's interface.	simont	7896d 18h	/8051/trunk/rtl/verilog/oc8051_uart.v
115	change uart to meet timing.	simont	7896d 20h	/8051/trunk/rtl/verilog/oc8051_uart.v
82	replace some modules	simont	7980d 19h	/8051/trunk/rtl/verilog/oc8051_uart.v
46	prepared header	simont	8085d 16h	/8051/trunk/rtl/verilog/oc8051_uart.v
36	fix bugs in mode 0	simont	8112d 18h	/8051/trunk/rtl/verilog/oc8051_uart.v
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8123d 21h	/8051/trunk/rtl/verilog/oc8051_uart.v
17	fix some bugs	simont	8129d 20h	/8051/trunk/rtl/verilog/oc8051_uart.v
10	% replaced with ^ in uart; some minor improvements	markom	8131d 00h	/8051/trunk/rtl/verilog/oc8051_uart.v
8	some IDS optimizations	markom	8132d 17h	/8051/trunk/rtl/verilog/oc8051_uart.v
5	more linter corrections; 2 tests still fail	markom	8132d 20h	/8051/trunk/rtl/verilog/oc8051_uart.v
4	Code repaired to satisfy the linter; testbech fails	markom	8132d 22h	/8051/trunk/rtl/verilog/oc8051_uart.v
2	Initial CVS import	simont	8148d 20h	/8051/trunk/rtl/verilog/oc8051_uart.v