URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Rev 180

Rev	Log message	Author	Age	Path
175	Corrected RS-232 pin connections. Cleaned up code. Removed debug code. System boots but the baud clock must be wrong - get garbage on hyperterm.	davidgb	1419d 06h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
174	Added button debounce. Single-step button. multiplex LED to show nibbles of addr and data for debug. Confirmed that CPU is reading from sys09swt.vhd SBug ROM correctly. Still need to debug ACIA output.	davidgb	1419d 10h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
173	Add another 16k BRAM for 56K total memory	davidgb	1421d 05h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
170	More debugging. Can now see cpu_addr incrementing correctly. Added 32k BRAM 0000-7FFF.	davidgb	1421d 11h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
169	Fixed clock connection and reset button polarity. Debug LED counting and cpu_clk now indicates some activity.	davidgb	1421d 17h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
162	stripped down to most basic system (no vdu, keyboard, sdram, ide, etc).	davidgb	1422d 06h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
148	Check in Atlys work	davidgb	1665d 21h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
141	Started work on version for Digilent Atlys SPARTAN6 board (does not build, just infrastructure to start the project)	davidgb	1701d 14h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd