URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.xise] - Rev 177

Rev	Log message	Author	Age	Path
175	Corrected RS-232 pin connections. Cleaned up code. Removed debug code. System boots but the baud clock must be wrong - get garbage on hyperterm.	davidgb	1935d 17h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
174	Added button debounce. Single-step button. multiplex LED to show nibbles of addr and data for debug. Confirmed that CPU is reading from sys09swt.vhd SBug ROM correctly. Still need to debug ACIA output.	davidgb	1935d 20h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
173	Add another 16k BRAM for 56K total memory	davidgb	1937d 16h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
170	More debugging. Can now see cpu_addr incrementing correctly. Added 32k BRAM 0000-7FFF.	davidgb	1937d 21h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
158	switch to stock SWT boot rom and flex9ram	davidgb	1938d 22h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
152	More atlys cleanup	davidgb	2182d 07h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
148	Check in Atlys work	davidgb	2182d 08h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
146		davidgb	2183d 20h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
141	Started work on version for Digilent Atlys SPARTAN6 board (does not build, just infrastructure to start the project)	davidgb	2218d 01h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise