URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [acia6850.vhd] - Rev 212

Rev	Log message	Author	Age	Path
197	Updates from John Kent: -- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect. -- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk -- for 125MHz Clock on Zybo Z7 board.	davidgb	1398d 18h	/System09/trunk/rtl/VHDL/acia6850.vhd
139	format	davidgb	1688d 23h	/System09/trunk/rtl/VHDL/acia6850.vhd
138	Remove DOS format	davidgb	1689d 00h	/System09/trunk/rtl/VHDL/acia6850.vhd
118	Update components to be compatible with Terasic DE1 implementation	dilbert57	5129d 12h	/System09/trunk/rtl/VHDL/acia6850.vhd
100	Updates from John. Digilent S3STARTER and XSA-3S1000 work.	davidgb	5194d 14h	/System09/trunk/rtl/VHDL/acia6850.vhd