URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [tags/] [ADS_RELEASE_3_0_0/] [Hardware/] [actel_ujtag/] [rtl/] [verilog/] [actel_ujtag.v] - Rev 68

Rev	Log message	Author	Age	Path
64	Rev. 3.0.0.	nyawn	4596d 03h	/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/actel_ujtag/rtl/verilog/actel_ujtag.v
42	Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation.	nyawn	5234d 09h	/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/actel_ujtag/rtl/verilog/actel_ujtag.v