URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_module.v] - Rev 69

Rev	Log message	Author	Age	Path
42	Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation.	nyawn	5175d 13h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
32	Added a hi-speed mode via a change in protocol in the adv_dbg_if core. This should provide an order-of-magnitude speed improvement for some USB JTAG cables. Updated adv_jtag_bridge to match. Updated adv_dbg_if testbenches. Updated documents to reflect the new hi-speed mode. Added alternate USB-Blaster driver based on libftdi, donated by Xianfeng Zeng. Various bugfixes.	nyawn	5248d 06h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
8	Moved sub-modules to the correct subdirectories.	nyawn	5492d 06h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
3	HDL cores which make up the hardware portion of the Advanced Debug System.	nyawn	5492d 06h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v