URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [syncreg.v] - Rev 42

Rev	Log message	Author	Age	Path
42	Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation.	nyawn	5339d 16h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/syncreg.v