URL https://opencores.org/ocsvn/ae18/ae18/trunk

Subversion Repositories ae18

[/] [ae18/] [trunk/] [rtl/] [verilog/] [ae18_core.v] - Rev 20

Rev	Log message	Author	Age	Path
20	New directory structure.	root	5745d 04h	/ae18/trunk/rtl/verilog/ae18_core.v
18	Fixed CPFSLT/CPFSGT bug discovered by G. M. Gallant.	sybreon	6260d 04h	/ae18/trunk/rtl/verilog/ae18_core.v
17	Moved testbench into sim/verilog/testbench.v Minor cleanup.	sybreon	6441d 00h	/ae18/trunk/rtl/verilog/ae18_core.v
15	Fixed various bugs: - STATUS,C not correct for subtraction instructions - Data memory indirect addressing mode bugs - Other minor fixes	sybreon	6451d 00h	/ae18/trunk/rtl/verilog/ae18_core.v
12	Rearranged code to make it synthesisable.	sybreon	6480d 23h	/ae18/trunk/rtl/verilog/ae18_core.v
10	Minor code clean up	sybreon	6546d 04h	/ae18/trunk/rtl/verilog/ae18_core.v
4	Minor bug fix for PCL read/write	sybreon	6546d 05h	/ae18/trunk/rtl/verilog/ae18_core.v
3	Minor bug fix.	sybreon	6546d 14h	/ae18/trunk/rtl/verilog/ae18_core.v
2	initial checkin	sybreon	6547d 07h	/ae18/trunk/rtl/verilog/ae18_core.v