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[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] [aeMB_ctrl.v] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5749d 02h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
77	This commit was manufactured by cvs2svn to create branch 'AEMB2_712'.		6207d 01h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
72	Minor code cleanup.	sybreon	6214d 04h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
65	Fixed minor typo causing synthesis failure.	sybreon	6229d 11h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
62	Fixed minor typo.	sybreon	6229d 21h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6229d 22h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6234d 04h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
53	Added GET/PUT support through a FSL bus.	sybreon	6235d 00h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6236d 03h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
50	Parameterised optional components.	sybreon	6236d 06h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6242d 01h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6242d 17h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_ctrl.v