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[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] [aeMB_xecu.v] - Rev 203

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5626d 21h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
77	This commit was manufactured by cvs2svn to create branch 'AEMB2_712'.		6084d 21h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
72	Minor code cleanup.	sybreon	6091d 23h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
66	Added fsl_tag_o to FSL bus (tag either address or data).	sybreon	6105d 18h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6107d 18h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6111d 23h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
53	Added GET/PUT support through a FSL bus.	sybreon	6112d 19h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
50	Parameterised optional components.	sybreon	6114d 02h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
45	Minor code cleanup.	sybreon	6119d 07h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6119d 20h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6120d 12h	/aemb/branches/AEMB2_712/rtl/verilog/aeMB_xecu.v