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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] [verilog/] [edk32.v] - Rev 203

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5730d 22h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
77	This commit was manufactured by cvs2svn to create branch 'AEMB2_712'.		6188d 22h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
73	Moved simulation kernel into code.	sybreon	6196d 00h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6205d 23h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
67	Minor simulation fixes.	sybreon	6207d 21h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6211d 19h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6212d 18h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
53	Added GET/PUT support through a FSL bus.	sybreon	6216d 20h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
50	Parameterised optional components.	sybreon	6218d 03h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
49	Added random seed for simulation.	sybreon	6221d 06h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6223d 22h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6224d 14h	/aemb/branches/AEMB2_712/sim/verilog/edk32.v