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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] [aeMB2_aslu.v] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5695d 00h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
115	This commit was manufactured by cvs2svn to create branch 'DEV_SYBREON'.		6027d 03h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
114	changed MSR bits	sybreon	6027d 03h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
101	Made multiplier pause with pipeline	sybreon	6119d 23h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
100	multiplier issues	sybreon	6119d 23h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
90	Fixed Carry bit bug.	sybreon	6143d 06h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
88	Minor optimisations.	sybreon	6143d 22h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
86	Some optimisations.	sybreon	6144d 15h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
82	Further optimisations (speed + size).	sybreon	6146d 21h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
81	Code cleanup + minor speed regression.	sybreon	6146d 22h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
80	Minor optimisations (~10% faster)	sybreon	6147d 23h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
78	initial import	sybreon	6149d 18h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v