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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] [aeMB2_aslu.v] - Rev 194

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5624d 17h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
115	This commit was manufactured by cvs2svn to create branch 'DEV_SYBREON'.		5956d 20h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
114	changed MSR bits	sybreon	5956d 20h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
101	Made multiplier pause with pipeline	sybreon	6049d 17h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
100	multiplier issues	sybreon	6049d 17h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
90	Fixed Carry bit bug.	sybreon	6072d 23h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
88	Minor optimisations.	sybreon	6073d 15h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
86	Some optimisations.	sybreon	6074d 08h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
82	Further optimisations (speed + size).	sybreon	6076d 14h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
81	Code cleanup + minor speed regression.	sybreon	6076d 16h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
80	Minor optimisations (~10% faster)	sybreon	6077d 17h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v
78	initial import	sybreon	6079d 11h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB2_aslu.v