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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] [aeMB_core.v] - Rev 195

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5602d 11h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
115	This commit was manufactured by cvs2svn to create branch 'DEV_SYBREON'.		5934d 14h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
71	Old version deprecated.	sybreon	6074d 16h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6106d 11h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
38	Added interrupt support.	sybreon	6251d 11h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
36	Removed asynchronous reset signal.	sybreon	6264d 21h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6285d 06h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
22	Added support for 8-bit and 16-bit data types.	sybreon	6286d 08h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6301d 01h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
11	Removed unused signals	sybreon	6308d 00h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v
3	initial import	sybreon	6333d 12h	/aemb/branches/DEV_SYBREON/rtl/verilog/aeMB_core.v