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[/] [aemb/] [tags/] [AEMB_711/] [rtl/] [verilog/] [aeMB_edk32.v] - Rev 192

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Rev	Log message	Author	Age	Path
191	New directory structure.	root	5624d 19h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
75	This commit was manufactured by cvs2svn to create tag 'AEMB_711'.		6089d 21h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
73	Moved simulation kernel into code.	sybreon	6089d 21h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
66	Added fsl_tag_o to FSL bus (tag either address or data).	sybreon	6103d 16h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
62	Fixed minor typo.	sybreon	6105d 15h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6105d 16h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6109d 21h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
53	Added GET/PUT support through a FSL bus.	sybreon	6110d 17h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6111d 20h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
50	Parameterised optional components.	sybreon	6112d 00h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
45	Minor code cleanup.	sybreon	6117d 05h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6117d 19h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6118d 10h	/aemb/tags/AEMB_711/rtl/verilog/aeMB_edk32.v

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