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[/] [aemb/] [tags/] [AEMB_711/] [sim/] [verilog/] [edk32.v] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5624d 22h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
75	This commit was manufactured by cvs2svn to create tag 'AEMB_711'.		6089d 23h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
73	Moved simulation kernel into code.	sybreon	6089d 23h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6099d 22h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
67	Minor simulation fixes.	sybreon	6101d 20h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6105d 18h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6106d 17h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
53	Added GET/PUT support through a FSL bus.	sybreon	6110d 19h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
50	Parameterised optional components.	sybreon	6112d 02h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
49	Added random seed for simulation.	sybreon	6115d 05h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6117d 21h	/aemb/tags/AEMB_711/sim/verilog/edk32.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6118d 13h	/aemb/tags/AEMB_711/sim/verilog/edk32.v