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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] [verilog/] [aeMB_aslu.v] - Rev 206

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5627d 17h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6290d 02h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
36	Removed asynchronous reset signal.	sybreon	6290d 02h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
31	Removed byte acrobatics.	sybreon	6306d 20h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6310d 11h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
24	Made minor performance optimisations.	sybreon	6310d 21h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
22	Added support for 8-bit and 16-bit data types.	sybreon	6311d 13h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6326d 07h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
7	Added CMP instruction	sybreon	6333d 05h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
5	Fixed endian correction issues on data bus.	sybreon	6333d 21h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v
3	initial import	sybreon	6358d 18h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_aslu.v