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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] [verilog/] [aeMB_control.v] - Rev 206

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5601d 23h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6264d 09h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
36	Removed asynchronous reset signal.	sybreon	6264d 09h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6265d 05h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6284d 17h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6300d 13h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
14	Added initial interrupt/exception support.	sybreon	6307d 04h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v
3	initial import	sybreon	6333d 00h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_control.v