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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] [verilog/] [aeMB_core.v] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5702d 08h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6364d 18h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
36	Removed asynchronous reset signal.	sybreon	6364d 18h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6385d 03h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
22	Added support for 8-bit and 16-bit data types.	sybreon	6386d 05h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6400d 23h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
11	Removed unused signals	sybreon	6407d 21h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v
3	initial import	sybreon	6433d 09h	/aemb/tags/AEMB_7_05/rtl/verilog/aeMB_core.v