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[/] [aemb/] [tags/] [AEMB_7_05/] [sim/] [verilog/] [testbench.v] - Rev 206

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5671d 13h	/aemb/tags/AEMB_7_05/sim/verilog/testbench.v
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6333d 22h	/aemb/tags/AEMB_7_05/sim/verilog/testbench.v
31	Removed byte acrobatics.	sybreon	6350d 15h	/aemb/tags/AEMB_7_05/sim/verilog/testbench.v
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6353d 16h	/aemb/tags/AEMB_7_05/sim/verilog/testbench.v
22	Added support for 8-bit and 16-bit data types.	sybreon	6355d 09h	/aemb/tags/AEMB_7_05/sim/verilog/testbench.v
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6368d 11h	/aemb/tags/AEMB_7_05/sim/verilog/testbench.v