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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_edk32.v] - Rev 191

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Rev Log message Author Age Path
191 New directory structure. root 5578d 19h /aemb/trunk/rtl/verilog/aeMB_edk32.v
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 5993d 22h /aemb/trunk/rtl/verilog/aeMB_edk32.v
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6018d 16h /aemb/trunk/rtl/verilog/aeMB_edk32.v
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6020d 17h /aemb/trunk/rtl/verilog/aeMB_edk32.v
73 Moved simulation kernel into code. sybreon 6043d 21h /aemb/trunk/rtl/verilog/aeMB_edk32.v
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6057d 16h /aemb/trunk/rtl/verilog/aeMB_edk32.v
62 Fixed minor typo. sybreon 6059d 15h /aemb/trunk/rtl/verilog/aeMB_edk32.v
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6059d 16h /aemb/trunk/rtl/verilog/aeMB_edk32.v
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6063d 21h /aemb/trunk/rtl/verilog/aeMB_edk32.v
53 Added GET/PUT support through a FSL bus. sybreon 6064d 17h /aemb/trunk/rtl/verilog/aeMB_edk32.v
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6065d 20h /aemb/trunk/rtl/verilog/aeMB_edk32.v
50 Parameterised optional components. sybreon 6066d 00h /aemb/trunk/rtl/verilog/aeMB_edk32.v
45 Minor code cleanup. sybreon 6071d 05h /aemb/trunk/rtl/verilog/aeMB_edk32.v
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6071d 19h /aemb/trunk/rtl/verilog/aeMB_edk32.v
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6072d 11h /aemb/trunk/rtl/verilog/aeMB_edk32.v

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