URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_ibuf.v] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5578d 17h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
105	Patch interrupt bug.	sybreon	5992d 11h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
103	Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)	sybreon	5993d 20h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
96	Stalls pipeline on MUL/BSF instructions results in minor speed improvements.	sybreon	6018d 14h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
70	Change interrupt to positive level triggered interrupts.	sybreon	6051d 21h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
63	Fixed interrupt signal synchronisation.	sybreon	6059d 12h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6059d 14h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6063d 19h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
45	Minor code cleanup.	sybreon	6071d 03h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6071d 17h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6072d 09h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v